关于原子操作
/* According to the Intel documentation the following operations are
atomic on the Intel Architecture processors:
- Reading or writing a byte.
- Reading or writing a word aligned on a 16-bit boundary.
- Reading or writing a doubleword aligned on a 32-bit boundary.
The compiler takes care of proper alignment so we don't have to
worry about unaligned access.
Bus-locking may be necessary for certain operations to be atomic on
multiprocessor machines. According to the Intel documentation this
is necessary for the following operations:
- The bit test and modify instructions (BTS, BTR and BTC).
- The exchange instructions (XADD, CMPXCHG, CMPXCHG8B).
- The following single-operand arithmetic and logical instructions:
INC, DEC, NOT, and NEG.
- The following two-operand arithmetic and logical instructions:
ADD, ADC, SUB, SBB, AND, OR, and XOR.
The XCHG instruction is automatically locked. */
atomic on the Intel Architecture processors:
- Reading or writing a byte.
- Reading or writing a word aligned on a 16-bit boundary.
- Reading or writing a doubleword aligned on a 32-bit boundary.
The compiler takes care of proper alignment so we don't have to
worry about unaligned access.
Bus-locking may be necessary for certain operations to be atomic on
multiprocessor machines. According to the Intel documentation this
is necessary for the following operations:
- The bit test and modify instructions (BTS, BTR and BTC).
- The exchange instructions (XADD, CMPXCHG, CMPXCHG8B).
- The following single-operand arithmetic and logical instructions:
INC, DEC, NOT, and NEG.
- The following two-operand arithmetic and logical instructions:
ADD, ADC, SUB, SBB, AND, OR, and XOR.
The XCHG instruction is automatically locked. */
